In recent years, various studies have been made for a semiconductor integrated circuit because of high integration, acceleration, and low power consumption. Particularly, in the case of a semiconductor integrated circuit having a MOS FET (Metal Oxide Semiconductor Field Effect Transistor), it is necessary to further fine devices and wirings in order to improve the device integration degree and the operation speed and, therefore, scaling of a device size is rapidly progressed.
The present inventor studied scaling of a semiconductor integrated circuit. The following is an art studied by the present inventor and its outline is described below.
That is, scaling of a semiconductor integrated circuit such as an LSI (Large Scale Integrated Circuit) includes two types--constant-voltage scaling and constant-electric-field scaling.
In the case of a CMOS semiconductor integrated circuit including a CMOS FET as a component, the constant-electric-field scaling is mainly executed from the viewpoint of securing the reliability of a gate oxide film. In this case, it is also necessary to lower a power supply voltage proportionally to reduction of a device size from the viewpoint of securing the stability of a device characteristic.
The literature on the fabrication art for a CMOS semiconductor integrated circuit is shown, for example, in W. MALY "ZUSETSU CHO ERUESUAI KOGAKU (transliterated)", pp. 167-191, issued by KEIGAKU SHUPPAN (transliterated) Co., Ltd. on Dec. 15, 1990. An original text of the above-transliterated literature is "Atlas of IC Technologies: An Introduction to VLSI Processes" by W. Maly (Copyright.COPYRGT. 1987 by The Benjamin/Cummings Publishing Company Inc.).
In the case of the above CMOS semiconductor integrated circuit, to make a scaling rule practically effective, it is necessary to lower a threshold voltage proportionally to a device size. This is because a voltage component contributing to a circuit operation can be shown by the expression of "power supply voltage-threshold voltage".
However, because lowering of a threshold voltage causes increase of leak current, a leak current test (I ddq test) widely used for the test of a semiconductor integrated circuit cannot be executed and, moreover, in the case of an aging test, temperature is extremely raised due to increase of the leak current and thereby, a problem of causing thermal runaway occurs.
FIG. 29 shows the mechanism of thermal runaway in the case of an aging test. In FIG. 29, x-axis shows the set junction temperature (junction temperature Tj1) of a semiconductor integrated circuit and y-axis shows the temperature (junction temperature Tj2) obtained by adding a temperature rise due to the total leak current of a semiconductor integrated circuit produced due to the junction temperature Tj1 to an ambient temperature. Normally, the junction temperature Tj2 and the junction temperature Tj1 are stabilized at an equal temperature. However, when a leak current component increases, temperature is extremely raised due to the leak current and resultingly, thermal runaway occurs.
By applying a back bias to the well of a MOS FET in order to solve the above problem, it is possible to consider a technique for controlling a threshold voltage.
In the case of this technique, however, the well potential may fluctuate due to noises under practical use (under normal operation) and a problem may occur in which a forward current is applied between the well and the source/drain to cause the latch-up phenomenon.
Moreover, the art for decreasing a leak current by using the back bias is described in, for example, the official gazette of Japanese Patent Laid-Open No. 6-334010/1994 which discloses a structure in which the substrate node of a low-threshold-voltage field effect transistor constituting a group of logic circuits to a power supply line and a dummy power supply line connected to the group of logic circuits to a power supply line through a high-threshold-voltage field effect transistor.
In the case of this art, the field effect transistor whose substrate node is connected to the power supply line can perform normal operation at a low threshold voltage by turning on the high-threshold-voltage transistor under the normal operation of a semiconductor integrated circuit while the low-threshold-voltage field effect transistor can temporarily have a high threshold voltage by turning off the high-threshold-voltage field effect transistor and applying a test voltage to the dummy power supply line.
However, this art has a problem that the circuit impedance increases and thereby, the general operation speed of the semiconductor integrated circuit lowers because the high-threshold-voltage field effect transistor is set between the group of logic circuits and the power supply in series.
Moreover, the official gazette of Japanese Patent Laid-Open No. 8-17183/1996 discloses an art of using switching means for making the substrate potential of a MOS FET variable as an art for controlling the threshold voltage of the MOS FET. This art makes it possible to switch the switching characteristic and the sub-threshold current characteristic because switching means switches the back gate bias of the MOS FET to first or second potential and absolute values of the threshold voltage of the MOS FET.
In the case of this art, however, the source and n-well of a p-channel MOS FET are short-circuited each other through an n-channel MOS FET. Therefore, problems occur that (1) it is necessary to generate a voltage higher than a power supply voltage under normal operation and (2) device characteristics are deteriorated because the high voltage in the above Item (1) is applied to the MOS FET and thereby, the thickness of the gate oxide film of the MOS FET must be increased.
It is an object of the present invention to provide a high-performance CMOS semiconductor integrated circuit capable of preventing the latch-up phenomenon and its fabrication art.
Moreover, it is another object of the present invention to provide an art capable of preventing the latch-up phenomenon of a CMOS semiconductor integrated circuit from occurring under the normal operation of the semiconductor integrated circuit and a leak current from being generated under the test of the circuit.
Furthermore, it is still another object of the present invention to provide an art capable of improving the reliability of a CMOS semiconductor integrated circuit under the normal operation and test without lowering the operation speed of the semiconductor integrated circuit under the normal operation of the circuit.
Furthermore, it is still another object of the present invention to provide an art capable of improving the reliability of a CMOS semiconductor integrated circuit under the normal operation and test of the circuit without deteriorating device characteristics.
The above and other objects and novel characteristic of the present invention will become more apparent from the following description when taken in conjunction with the accompanying drawings.